Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device
US6410388B1 · kind B1 · utility
36Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Jul 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A process for fabricating a memory cell in a two-bit EEPROM device, includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with a p-type dopant, wherein the resist mask is used as an ion implant mask, and annealing the semiconductor substrate before implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the annealing of the semiconductor substrate laterally diffuses the p-type dopants to form pocket regions on either side of the EEPROM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.