Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization
US6410399B1 · kind B1 · utility
9Cited by
11References
17Claims
0Family size
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Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Jun 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.