Herbert L. Ho
117Patents
23h-index
171Co-inventors
93Inventor score
Filing activity: Oct 29, 1993 → Jun 23, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7118986B2 | STI formation in semiconductor device including SOI and bulk silicon regions | Electricity | 240 | Expired |
| US5447884A | Shallow trench isolation with thin nitride liner | Emerging Cross-Sectional Technologies | 168 | Expired |
| US6319794A | Structure and method for producing low leakage isolation devices | Electricity | 135 | Expired |
| US8129797B2 | Work function engineering for eDRAM MOSFETs | Electricity | 119 | Active |
| US5763315A | Shallow trench isolation with oxide-nitride/oxynitride liner | Electricity | 109 | Expired |
| US6046487A | Shallow trench isolation with oxide-nitride/oxynitride liner | Electricity | 90 | Expired |
| US5876788A | High dielectric TiO.sub.2 -SiN composite films for memory applications | Electricity | 64 | Expired |
| US5827765A | Buried-strap formation in a dram trench capacitor | Electricity | 60 | Expired |
| US6140208A | Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications | Electricity | 45 | Expired |
| US5670805A | Controlled recrystallization of buried strap in a semiconductor memory device | Electricity | 42 | Expired |
| US7816728B2 | Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications | Electricity | 39 | Expired |
| US5643823A | Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures | Emerging Cross-Sectional Technologies | 38 | Expired |
| US8008713B2 | Vertical SOI trench SONOS cell | Electricity | 35 | Active |
| US7276751B2 | Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same | Electricity | 32 | Expired |
| US5656535A | Storage node process for deep trench-based DRAM | Emerging Cross-Sectional Technologies | 31 | Expired |
| US5543348A | Controlled recrystallization of buried strap in a semiconductor memory device | Electricity | 30 | Expired |
| US6964897B2 | SOI trench capacitor cell incorporating a low-leakage floating body array transistor | Electricity | 29 | Expired |
| US5747866A | Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures | Emerging Cross-Sectional Technologies | 29 | Expired |
| US5356837A | Method of making epitaxial cobalt silicide using a thin metal underlayer | Electricity | 29 | Expired |
| US8120095B2 | High-density, trench-based non-volatile random access SONOS memory SOC applications | Physics | 27 | Active |
| US5792685A | Three-dimensional device layout having a trench capacitor | Electricity | 27 | Expired |
| US5844266A | Buried strap formation in a DRAM trench capacitor | Electricity | 24 | Expired |
| US6297127A | Self-aligned deep trench isolation to shallow trench isolation | Electricity | 23 | Expired |
| US5893735A | Three-dimensional device layout with sub-groundrule features | Electricity | 21 | Expired |
| US6815749B1 | Backside buried strap for SOI DRAM trench capacitor | Electricity | 21 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.