Recess metallization via selective insulator formation on nucleation/seed layer
US6410418B1 · kind B1 · utility
33Cited by
6References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein “pinching-off” of the recess opening due to formation of overhanging metal deposits as a result of increased rate of electrodeposition thereat is prevented. Embodiments include preliminarily selectively rendering the recess opening surface non-conductive. The inventive method also enables a reduction in electrodeposition over non-recessed areas, thereby reducing the time required for planarization, as by CMP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.