Semiconductor wafer alignment method using an identification scribe
US6410927B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 1999 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Apr 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for detecting defects in both processed and unprocessed (blank) wafers, a manufacturer's identification mark is used to align wafers during inspection. The wafers, are subject to an initial scan under low magnification using an inspection tool and transferred to a high magnification analysis tool for more complete analysis. Prior to scanning, the wafers are oriented using the manufacturer's identification mark. The wafers become misaligned when transferred between tools. Using the manufacturer's identification mark, the wafers are reoriented and aligned. During scanning, defects in the wafer surface are located. The location of all defects are referenced to the location of the manufacturer's identification mark. To easily find defects when a wafer is transferred from tool to tool, the manufacturer's identification mark is located and, using a software algorithm, the wafer is oriented and aligned to the mark each time it is transferred and inspected. When placed in an analysis tool, the software algorithm aligns the wafer using the manufacturer's identification mark. This allows the analysis tool to navigate directly to the desired features (i.e. defects) without wasting…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.