Memory cell arrays comprising intersecting slanted portions

US6410948B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Luan C. Tran · Meridian, US
• D. Mark Duncan · Boise, US
• Tyler Lowrey · San Jose, US
• Rob B. Kerr · Boise, US
• Kris K. Brown · Garden City, US

Key dates

• Filing date: Jun 28, 1999
• Grant date: Jun 25, 2002
• Expiry date: Jun 28, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/482

Abstract

A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.