Mask, structures, and method for calibration of patterned defect inspections
US6411378B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N21/956
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
There is provided an on-wafer apparatus and method for calibrating the sensitivity of a patterned wafer defect inspection tool during set-up which is used to detect defects on the surface of a semiconductor wafer during the stages of a fabrication process. A semiconductor wafer which is to be inspected for defects is provided. A calibration structure having known defects is introduced on a selected area of the semiconductor wafer which is to be inspected prior to, the inspection. The calibration structure includes a plurality of intentionally-introduced defects each being of a progressively smaller size dimension. Calibration of the sensitivity of the defect inspection tool is accomplished by scanning the semiconductor wafer with the calibration structure in order to determine the defects which are known to exist. As a result, there is provided a universal calibration method which allows an operator to know the smallest size defect which is detected by the defect inspection tool for each inspection in the fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.