Quad flat non-lead package of semiconductor
US6414385B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Quad Flat Non-Lead package of semiconductor comprises a chip, a plurality of leads, and a molding compound. The chip has its active surface bonded to the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pad on the active surface of the chip. The leads are disposed at the periphery of the die pad. A plurality of bonding wires is used to electrically connect the top surface of the leads to the bonding pads. The molding compound encapsulates the chip, the die pad, the bonding wires, and a portion of the surface of the leads. In this way, the encapsulating process make the side surface of the lead, and the portion excluding the wire-bonding protruded zone of the bottom surface of the lead exposed in order to make the leads become the external connections of the package structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.