Dual-damascene interconnect structures and methods of fabricating same
US6417094B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1998 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Dec 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1031
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect fabrication process and structure provides barrier enhancement at the via sidewalls and improved capability to fabricate high aspect ratio dual damascene interconnects. A via structure is patterned into the via dielectric first, then a dielectric barrier (for example, anisotropically etched silicon nitride) is formed only along the via sidewalls in the dual damascene structure prior to deposition of a metal barrier (for example, Ta/TaN). In this way, the effective barrier thickness along the bottom of the via is increased, eliminating the structure's susceptibility to metal migration. The absence of dielectric barrier along the interconnect trench sidewalls leads to low interconnect resistance and low interconnect capacitance. The present invention also provides an improved fabrication method for obtaining high aspect ratio dual damascene interconnect structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.