Void eliminating seed layer and conductor core integrated circuit interconnects
US6417566B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2000 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Nov 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seed layer is disposed between the barrier layer and the conductor core. The seed layer has an associated element which is formed during annealing into an intermetallic compound which has a density lower than the density of the conductor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.