Amit P. Marathe
58Patents
13h-index
50Co-inventors
87Inventor score
Filing activity: Oct 27, 1998 → Jul 29, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6952052B1 | Cu interconnects with composite barrier layers for wafer-to-wafer uniformity | Electricity | 40 | Expired |
| US6599827B1 | Methods of forming capped copper interconnects with improved electromigration resistance | Electricity | 25 | Expired |
| US7084062B1 | Use of Ta-capped metal line to improve formation of memory element films | Electricity | 24 | Expired |
| US6822437B1 | Interconnect test structure with slotted feeder lines to prevent stress-induced voids | Electricity | 20 | Expired |
| US7310155B1 | Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures | Physics | 20 | Expired |
| US7451411B2 | Integrated circuit design system | Physics | 20 | Active |
| US6506677B1 | Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance | Electricity | 18 | Expired |
| US6433402B1 | Selective copper alloy deposition | Electricity | 17 | Expired |
| US6531777B1 | Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP | Electricity | 16 | Expired |
| US6432822B1 | Method of improving electromigration resistance of capped Cu | Electricity | 16 | Expired |
| US6725433B1 | Method for assessing the reliability of interconnects | Physics | 15 | Expired |
| US6075293A | Semiconductor device having a multi-layer metal interconnect structure | Electricity | 15 | Expired |
| US6309959A | Formation of self-aligned passivation for interconnect to minimize electromigration | Electricity | 14 | Expired |
| US6498384B1 | Structure and method of semiconductor via testing | Emerging Cross-Sectional Technologies | 13 | Expired |
| US6822473B1 | Determination of permeability of layer material within interconnect | Physics | 13 | Expired |
| US6426293B1 | Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant | Electricity | 12 | Expired |
| US6867056B1 | System and method for current-enhanced stress-migration testing of interconnect | Physics | 12 | Expired |
| US6727592B1 | Copper interconnect with improved barrier layer | Electricity | 10 | Expired |
| US6417566B1 | Void eliminating seed layer and conductor core integrated circuit interconnects | Electricity | 10 | Expired |
| US6897476B1 | Test structure for determining electromigration and interlayer dielectric failure | Electricity | 9 | Expired |
| US6858511B1 | Method of semiconductor via testing | Emerging Cross-Sectional Technologies | 9 | Expired |
| US6714037B1 | Methodology for an assessment of the degree of barrier permeability at via bottom during electromigration using dissimilar barrier thickness | Physics | 9 | Expired |
| US6531780B1 | Via formation in integrated circuit interconnects | Emerging Cross-Sectional Technologies | 9 | Expired |
| US7146588B1 | Predicting EM reliability by decoupling extrinsic and intrinsic sigma | Physics | 9 | Expired |
| US7288782B1 | Use of Ta-capped metal line to improve formation of memory element films | Electricity | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.