Full additive process with filled plated through holes
US6418616B2 · kind B2 · utility
12Cited by
18References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.