Three-dimensional memory array and method of fabrication
US6420215B1 · kind B1 · utility
824Cited by
18References
22Claims
0Family size
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Key dates
| Filing date | Mar 21, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Mar 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.