Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates
US6420250B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Mar 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.