Leadframe based chip scale package and method of producing the same
US6420779B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Sep 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention in a quad flat no-lead package is described. The package is produced by encapsulating an integrated circuit chip, a die pad to which the chip is affixed, and leads which are connected to the chip in a molding compound. Leads are positioned on all four sides of the package, the exposed (bottom) portions of the leads are coplanar with the bottom of the package, and the leads do not extend, or extend only slightly, beyond the area of the package. The package includes a die pad also having an exposed (bottom) portion that is coplanar with the bottom of the package. The top portions of the leads are coplanar with the top surface of the die pad, and are flat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.