Determination of thermal resistance for field effect transistor formed in SOI technology
US6423604B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2001 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | May 1, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The thermal resistance Rth parameter is determined for a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology. A p-n junction is formed with one of a drain region or a source region of the field effect transistor. The p-n junction is biased at a bias voltage. The p-n junction is heated to a plurality of temperatures. A current conducted through the p-n junction is measured at each of the plurality of temperatures of the p-n junction to generate a current versus temperature characteristic for the p-n junction. A respective current flowing through the p-n junction is measured as the field effect transistor is biased to dissipate each of a plurality of power dissipation levels and with the p-n junction being biased at the bias voltage. The respective temperature of the p-n junction is determined from the measured respective current and the current versus temperature characteristic for each of the plurality of power dissipation levels. The thermal resistance is determined to be a rate of change of temperature with respect to a rate of change of power dissipation level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.