Low temperature silicon wafer bond process with bulk material bond strength
US6423613B1 · kind B1 · utility
72Cited by
68References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 10, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Mar 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention includes a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing a first article that has a semiconductor surface and a second article that has a semiconductor surface. The semiconductor surfaces are annealed with an energy source wherein energy is confined to the semiconductor surfaces. The annealed surfaces are bonded to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.