Inventor · Berkeley Heights, NJ, US

Joseph E. Geusic

93Patents
37h-index
13Co-inventors
85Inventor score

Filing activity: Sep 4, 1980 → Jul 27, 2011

Most-cited inventions

PatentTitleAreaCited byStatus
US6630713B2 Low temperature silicon wafer bond process with bulk material bond strength Electricity 313 Expired
US6545314B2 Memory using insulator traps Electricity 309 Expired
US6025627A Alternate method and structure for improved floating gate tunneling devices Emerging Cross-Sectional Technologies 224 Expired
US5981350A Method for forming high capacitance memory cells Emerging Cross-Sectional Technologies 180 Expired
US6246606A Memory using insulator traps Electricity 148 Expired
US5886368A Transistor with silicon oxycarbide gate and methods of fabrication and use Electricity 121 Expired
US6356500B1 Reduced power DRAM device and method Physics 114 Expired
US6593656B2 Multilevel copper interconnects for ultra large scale integration Electricity 107 Expired
US6351411B2 Memory using insulator traps Electricity 103 Expired
US6025225A Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same Electricity 96 Expired
US6143616A Methods of forming coaxial integrated circuitry interconnect lines Electricity 92 Expired
US6249460A Dynamic flash memory cells with ultrathin tunnel oxides Physics 89 Expired
US6709978B2 Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer Electricity 86 Expired
US6090636A Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same Physics 86 Expired
US6294813A Information handling system having improved floating gate tunneling devices Emerging Cross-Sectional Technologies 86 Expired
US6150188A Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same Electricity 83 Expired
US6812513B2 Method and structure for high capacitance memory cells Emerging Cross-Sectional Technologies 83 Expired
US6140181A Memory using insulator traps Electricity 79 Expired
US6423613B1 Low temperature silicon wafer bond process with bulk material bond strength Electricity 72 Expired
US6198168A Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same Electricity 71 Expired
US6456535B2 Dynamic flash memory cells with ultra thin tunnel oxides Physics 65 Expired
US6331465A Alternate method and structure for improved floating gate tunneling devices using textured surface Emerging Cross-Sectional Technologies 64 Expired
US6526191B1 Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same Electricity 63 Expired
US6232643A Memory using insulator traps Electricity 63 Expired
US7084451B2 Circuits with a trench capacitor having micro-roughened semiconductor surfaces Electricity 57 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.