Lead-bond type chip package and manufacturing method thereof
US6423622B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2000 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections. This invention also provides a method of producing a multilayer substrate for use in forming a lead-bond type chip package
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.