Low Resistance package for semiconductor devices
US6423623B1 · kind B1 · utility
41Cited by
29References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Aug 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.