Method of forming low resistance metal silicide region on a gate electrode of a transistor

US6423634B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Karsten Wieczorek · Dresden, DE
• Michael Raab · Salem, DE
• Rolf Stephan · Dresden, DE

Key dates

• Filing date: Apr 25, 2000
• Grant date: Jul 23, 2002
• Expiry date: Apr 25, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.