Process for fabricating a metal-metal capacitor within an integrated circuit, and corresponding integrated circuit
US6423996B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2000 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Sep 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.