MRAM architecture using offset bits for increased write selectivity

US6424561B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Shaoping Li · Naperville, US
• Theodore Zhu · Maple Grove, US
• Anthony Arrott · Washington, US
• Harry Hongyue Liu · Maple Grove, US
• William Larson · Eden Prairie, US
• Yong Lu · Rosemount, US

Key dates

• Filing date: Jul 18, 2000
• Grant date: Jul 23, 2002
• Expiry date: Jul 18, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B61/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.