MRAM architectures for increased write selectivity
US6424564B1 · kind B1 · utility
6Cited by
10References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Sep 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.