System and method for reading data from a programmable logic device

US6425077B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Thach-Kinh Le · Monte Sereno, US
• Chakravarthy K. Allamsetty · San Jose, US
• Carl H. Carmichael · San Jose, US
• Arun K. Mandhania · San Jose, US
• Donald H. St. Pierre, Jr. · Nashua, US
• Conrad A. Theron · San Jose, US

Key dates

• Filing date: May 14, 1999
• Grant date: Jul 23, 2002
• Expiry date: May 14, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318516
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.