Auto correction of error checked simulated printed images
US6425112B1 · kind B1 · utility
220Cited by
12References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1999 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Jun 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer system are provided for checking integrated circuit designs for design rule violations. The method may include generating a working design data set, creating a wafer image data set, comparing the wafer image data set to the design rules to produce an error list and automatically altering the working design data set when the comparing indicates a design rule violation. The method further automatically repeats the creating, the comparing and the automatically altering until no design rule violations occur or no solution to the errors exists.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.