Method for etching passivation layers and antireflective layer on a substrate
US6426016B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1999 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Aug 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to etch passivation layers and an antireflective layer on a substrate, comprising: forming a metal layer on the substrate; forming the antireflective layer on the metal layer; forming the passivation layers on the antireflective layer, wherein the passivation layer consisting of a silicon oxide layer on the antireflective layer and a silicon nitride layer on the silicon oxide layer; etching the silicon nitride layer in a first etching chamber, wherein the silicon nitride layer is etched in a uniformity of less than 10% in the first etching chamber; etching the silicon oxide layer in a second etching chamber, wherein the silicon oxide layer is etching in a uniformity of less than 5% in the second etching chamber; etching the antireflective layer in the second etching chamber to expose a surface of the metal layer for metal contacts of integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.