Process for forming power MOSFET device in float zone, non-epitaxial silicon

US6426248B2 · kind B2 · utility

Assignee

• International Rectifier Corporation · US

Inventors

• Richard Francis · Manhattan Beach, US
• Chiu Ng · El Segundo, US

Key dates

• Filing date: Dec 11, 2000
• Grant date: Jul 30, 2002
• Expiry date: Dec 11, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/62

Abstract

A vertical conduction MOSFET semiconductor device is formed in a non-epitaxial (float zone) lightly doped silicon substrate. Device junction regions are formed in the top surface of the lightly doped float zone substrate. The backside of the wafer is then ground by surface grinding to attain a desired thickness. Phosphorus, or another N type dopant species, is then implanted into the back surface and is activated by a laser anneal. Back surface damage caused by grinding and/or implantation is intentionally retained. Alternatively, a “transparent” layer is formed by depositing highly doped amorphous silicon on the back surface. Titanium, or another metal (excluding aluminum), is then deposited on the back surface and annealed to form a titanium silicide, or other silicide for a contact electrode.