Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant
US6426293B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1089
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance and a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures. For forming an IC interconnect structure within an IC interconnect opening, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening, and the IC interconnect opening is filled by growing a fill conductive material from the alloy seed layer within the IC interconnect opening. A thermal anneal process is performed at a thermal anneal temperature. A desired thickness of the alloy seed layer, a desired concentration of the alloy dopant, and a desired thermal…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.