Method and apparatus for adaptive verification of circuit designs
US6427223B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1999 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Apr 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the monitoring of a device under test (DUT). The HVL language supports Object-Oriented Programming (or OOP). Within this OOP framework, the present invention provides a monitoring facility comprised of three main stages: i) Coverage Definitions, ii) Coverage Instantiation and Triggering and iii) Coverage Feedback. A coverage definition is very similar to an OOP class definition, but does not contain methods or variables. Instead, the basic purpose of a coverage definition is to declare “monitor bins” in terms of a state variable. Essentially, each monitor bin declaration has a unique bin name which is associated with a particular behavior of the state variable and the unique bin name is used to record the state variable's behavior. Instantiation of a coverage definition produces a coverage instance. Two key instantiation parameters are: an actual state variable that is to be monitored by the instance and a trigger expression which determines when the state variable of the instance is to be monitored. Instantiating means that a concurrent, non-terminating, “coverage i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.