Lead-frame-based chip-scale package and method of manufacturing the same
US6427976B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1999 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Dec 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead-frame-based chip-scale package (CSP) structure and a method of manufacturing the same are proposed. The proposed CSP structure is characterized in the use of a specially-designed lead frame having an inner-lead part and an outer-lead part, which each inner lead being formed with a deformed portion. During the encapsulation process, an epoxy molding compound (EMC) is formed to encapsulate the semiconductor die and the inner-lead part. By the proposed CSP structure, both sides of the inner-lead part can be wrapped by the EMC due to it being raised by the deformed portion to within the EMC. As a result, during the lead-singulation process, the inner-lead part can be firmly supported in position, thereby reducing the occurrence of micro cracks in the EMC above the inner-lead part that would otherwise occur in the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.