Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect

US6429068B1 · kind B1 · utility

Assignees

• International Business Machines Corporation · US
• Infineon Technologies North America Corp. · US

Inventors

• Ramachandra Divakaruni · Ossining, US
• Ulrike Gruening · Wappingers Falls, US
• Jack A. Mandelman · Stormville, US
• Larry Nesbit · Farmington, US
• Carl Radens · Lagrangeville, US

Key dates

• Filing date: Jul 2, 2001
• Grant date: Aug 6, 2002
• Expiry date: Jul 2, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.