Multiple active layer structure and a method of making such a structure
US6429484B1 · kind B1 · utility
309Cited by
23References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Aug 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
An integrated circuit includes multiple active layers. Preferably, a semiconductor-on-insulator (SOI) or silicon-on-insulator wafer is utilized to house a first active layer. A second active layer is provided above an insulative layer above the SOI substrate. Solid phase epitaxy can be used to form the second active layer. Subsequent active layers can be added by a similar technique. A seeding window can also be utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.