Multichip semiconductor package
US6429528B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip semiconductor package, and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconductor chips, instead of being singulated into a plurality of single-chip packages, are kept as integrally formed together and are thereafter electrically connected together so as to form a larger circuit. Encapsulated follows so as to form a single, multichip package. Common signals of the plurality of semiconductor chips are bussed together in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a PWB. The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the common electrode in contact therewith. The common electrode contacts the conductive lead through an opening formed in the encapsulant that surrounds the substrate. The extended portions of each conductive lead are staggered with respect to the extended portion of the co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.