Scratchpad RAM memory accessible in parallel to a primary cache
US6430655B1 · kind B1 · utility
40Cited by
5References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low-latency scratchpad RAM memory system is disclosed. The scratchpad RAM memory system can be accessed in parallel to a primary cache. Parallel access to the scratchpad RAM memory can be designed to be independent of a corresponding cache tag RAM, thereby enabling the scratchpad RAM memory to be sized to any specification, independent of the size of the primary cache data RAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.