Cache and management method using combined software and hardware congruence class selectors
US6430656B1 · kind B1 · utility
13Cited by
19References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1999 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory provides a mechanism for storing and retrieving values wherein a hardware mechanism such as a partial address field selector is combined with an software generated selector in order to access specific congruence classes within a cache. Assignment of software generated selectors to specific types of data can be made in order to allow an operating system or application to efficiently manage cache usage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.