Method of fabricating memory device and logic device on the same chip
US6432768B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Feb 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate. Ions are second implanted into the second region of the chip, by using the second gate as a mask, to form a second doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.