Method of fabricating memory cell with trench capacitor and vertical transistor
US6432774B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/053
Abstract
A method of fabricating a vertical transistor of a memory cell is disclosed. According to this method, a semiconductor substrate is first provided. A pad layer is formed over the substrate. Then, a deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is formed to fill the deep trench. The pad layer, the substrate, the first and the second conductive layers and the collar oxide layer are patterned. A first insulating layer is deposited to form the Shallow Trench Isolation. Both sides of the Shallow Trench Isolation and a portion of the second conductive layer are removed to form a buried strap and an opening. The pad layer is removed. A second insulating layer is formed over the substrate and the buried strap, and is removed after forming a well. A third insulating layer is formed on the substrate. After removing the third insulating layer on top surface of the substrate, the gate oxide is formed. Sequentially, a third conductive layer and a fourth conductive layer are formed to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.