Jeng-Ping Lin
33Patents
9h-index
38Co-inventors
75Inventor score
Filing activity: Jun 15, 1995 → Nov 12, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6734066B2 | Method for fabricating split gate flash memory cell | Electricity | 52 | Expired |
| US8343829B2 | Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same | Electricity | 23 | Active |
| US7994559B2 | Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same | Electricity | 22 | Active |
| US6794250B2 | Vertical split gate flash memory cell and method for fabricating the same | Electricity | 19 | Expired |
| US6800895B2 | Vertical split gate flash memory cell and method for fabricating the same | Electricity | 17 | Expired |
| US5536683A | Method for interconnecting semiconductor devices | Electricity | 17 | Expired |
| US6432774B1 | Method of fabricating memory cell with trench capacitor and vertical transistor | Electricity | 16 | Expired |
| US6355529B2 | Method of fabricating memory cell with vertical transistor | Electricity | 11 | Expired |
| US6696717B2 | Memory cell with vertical transistor and trench capacitor | Electricity | 9 | Expired |
| US6534359B2 | Method of fabricating memory cell | Electricity | 7 | Expired |
| US6781181B2 | Layout of a folded bitline DRAM with a borderless bitline | Electricity | 7 | Expired |
| US7541244B2 | Semiconductor device having a trench gate and method of fabricating the same | Electricity | 3 | Active |
| US7678692B2 | Fabrication method for a damascene bit line contact plug | Electricity | 3 | Active |
| US6801462B2 | Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices | Electricity | 3 | Expired |
| US6788598B2 | Test key for detecting overlap between active area and deep trench capacitor of a DRAM and detection method thereof | Electricity | 2 | Expired |
| US7109094B2 | Method for preventing leakage in shallow trench isolation | Electricity | 2 | Expired |
| US6743717B1 | Method for forming silicide at source and drain | Electricity | 2 | Expired |
| US11315928B2 | Semiconductor structure with buried power line and buried signal line and method for manufacturing the same | Electricity | 2 | Active |
| US7759190B2 | Memory device and fabrication method thereof | Electricity | 2 | Active |
| US7144799B2 | Method for pre-retaining CB opening | Electricity | 1 | Expired |
| US8395209B1 | Single-sided access device and fabrication method thereof | Electricity | 1 | Active |
| US6909136B2 | Trench-capacitor DRAM cell having a folded gate conductor | Electricity | 1 | Expired |
| US11002562B2 | Encoder using a magnetic sensing assembly and an optical sensing assembly and position detection method for a motor | Physics | 1 | Active |
| US7005698B2 | Split gate flash memory cell | Electricity | 1 | Expired |
| US6958521B2 | Shallow trench isolation structure | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.