Dense multi-gated device design

US6433372B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Eric Adler · Jericho, US
• Kerry Bernstein · Underhill, US
• John J. Ellis-Monaghan · Grand Isle, US
• Jenifer E. Lary · South Burlington, US
• Edward J. Nowak · South Burlington, US
• Norman J. Rohrer · Underhill, US

Key dates

• Filing date: Mar 17, 2000
• Grant date: Aug 13, 2002
• Expiry date: Mar 17, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/023

Abstract

A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.