Split-gate vertically oriented EEPROM device and process
US6433382B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1995 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Apr 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split-gate EEPROM transistor includes a channel region (22) formed in a vertically disposed semiconductor body (58) and residing intermediate to a drain region (26) and a source region (24). A select gate electrode (28) is horizontally disposed on a semiconductor substrate (20). A floating gate electrode (30) resides adjacent to the channel region (22) and overlies the select gate electrode (28). A control gate electrode (32) resides adjacent to the control gate electrode (30) and also overlies the select gate electrode (28). In operation, the select gate electrode (28) regulates the flow of electrical charge from the source region (24) into the channel region (22), and provides a field plate electrical isolation for adjacent memory cells in an EEPROM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.