Marius Orlowski
81Patents
19h-index
63Co-inventors
87Inventor score
Filing activity: Jun 27, 1991 → Sep 13, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5705415A | Process for forming an electrically programmable read-only memory cell | Electricity | 178 | Expired |
| US6433382B1 | Split-gate vertically oriented EEPROM device and process | Electricity | 150 | Expired |
| US7226833B2 | Semiconductor device structure and method therefor | Electricity | 122 | Expired |
| US6831350B1 | Semiconductor structure with different lattice constant materials and method for forming the same | Electricity | 78 | Expired |
| US5314834A | Field effect transistor having a gate dielectric with variable thickness | Emerging Cross-Sectional Technologies | 68 | Expired |
| US6921700B2 | Method of forming a transistor having multiple channels | Electricity | 66 | Expired |
| US7238580B2 | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration | Electricity | 43 | Expired |
| US5605855A | Process for fabricating a graded-channel MOS device | Electricity | 41 | Expired |
| US7339241B2 | FinFET structure with contacts | Electricity | 41 | Expired |
| US5741736A | Process for forming a transistor with a nonuniformly doped channel | Emerging Cross-Sectional Technologies | 37 | Expired |
| US8293608B2 | Intermediate product for a multichannel FET and process for obtaining an intermediate product | Electricity | 32 | Active |
| US7592248B2 | Method of forming semiconductor device having nanotube structures | Electricity | 32 | Active |
| US7221006B2 | GeSOI transistor with low junction current and low junction capacitance and method for making the same | Electricity | 32 | Expired |
| US7112832B2 | Transistor having multiple channels | Electricity | 31 | Expired |
| US7354831B2 | Multi-channel transistor structure and method of making thereof | Electricity | 30 | Active |
| US5432118A | Process for forming field isolation | Electricity | 24 | Expired |
| US7435639B2 | Dual surface SOI by lateral epitaxial overgrowth | Electricity | 20 | Active |
| US6573160B2 | Method of recrystallizing an amorphous region of a semiconductor | Electricity | 19 | Expired |
| US7037795B1 | Low RC product transistors in SOI semiconductor process | Electricity | 19 | Expired |
| US7238555B2 | Single transistor memory cell with reduced programming voltages | Physics | 16 | Expired |
| US7932189B2 | Process of forming an electronic device including a layer of discontinuous storage elements | Emerging Cross-Sectional Technologies | 14 | Active |
| US7288448B2 | Method and apparatus for mobility enhancement in a semiconductor device | Electricity | 14 | Expired |
| US7029980B2 | Method of manufacturing SOI template layer | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7608893B2 | Multi-channel transistor structure and method of making thereof | Electricity | 13 | Active |
| US5985736A | Process for forming field isolation | Electricity | 12 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.