Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same
US6433409B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, comprising: a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion; an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion; and a molding resin for sealing said joined portion including the solder, wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin, the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa, and the solder comprise gold/tin solder. This constitution contributes to an improved in reliability with respect to temperature cycling in lead-patterning substrates, semiconductor devices, and el…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.