Circuit configuration for reading a memory cell having a ferroelectric capacitor
US6434039B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Apr 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.