Device and method for repairing a semiconductor memory
US6434066B1 · kind B1 · utility
10Cited by
26References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Aug 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.