Two moment RC delay metric for performance optimization
US6434729B1 · kind B1 · utility
6Cited by
16References
15Claims
0Family size
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Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.