Semiconductor integrated circuit and method for manufacturing the same
US6436753B1 · kind B1 · utility
10Cited by
8References
1Claims
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Key dates
| Filing date | Aug 11, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Aug 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.