Semiconductor structure having a planar junction termination with high breakdown voltage and low parasitic capacitance
US6437416B1 · kind B1 · utility
1Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1996 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Apr 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/051
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The breakdown voltage of a semiconductor device, such as a transistor fabricated in a device region in and abutting the surface of a semiconductor body with a field oxide surrounding the device region, is improved by etching the field oxide abutting the device region to reduce the thickness thereof to about 0.6-1.4 &mgr;m and then forming a field plate in the recessed field oxide which is capacitively coupled to the underlying semiconductor body. The field plate can be floating, connected to a voltage potential, or connected to the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.