Making semiconductor devices having stacked dies with biased back surfaces
US6437449B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 6, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Apr 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20752
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has multiple, stacked dies in which the back surfaces of each die can be biased to the same or a different electrical potential. The device includes a substrate having a plurality of electrically conductive leads arrayed around an electrically conductive die-mounting pad. A first semiconductor die is mounted on and in electrical connection with the pad. A uniformly thin spacer is mounted on the first die inside the inner periphery of the wire bonding pads thereon and such that the spacer is electrically isolated from the first die. A second die is mounted on the spacer with a layer of electrically conductive material. The layer of conductive material and the die pad are electrically connected to the same or different leads of the substrate such that, by connecting the leads to the same or different electrical potentials, the respective back surfaces of the dies are biased to the same or different potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.