Patent · US Expired

Memory cell configuration

US6438022B2 · kind B2 · utility

11Cited by

7References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Till Schlosser · Dresden, DE
Wolfgang Krautschneider · Ottobrunn, DE
Franz Hofmann · Munich, DE
Thomas Haneder · Hersbruck, DE

Key dates

Filing date	May 10, 2001
Grant date	Aug 20, 2002
Priority date	—
Expiry date	May 10, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH10B53/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.